This invention relates generally to latch circuits. More particularly, the present invention relates to latch circuits including a non-volatile ferroelectric storage element.
Electrically programmable non-volatile information storage has been realized for some time using floating-gate charge storage mechanisms as in EPROM, EEPROM and FLASH memories. Although these technologies provide non-volatility, they require long programming times and high programming voltages. Additionally, the maximum number of read/write cycles is limited to about one hundred thousand (10.sup.5) cycles.
More recently, programmable non-volatile memories have been realized using ferroelectric materials such as lead zirconate titanate (PZT). Ferroelectric materials exhibit two stable polarization states that can be set and interrogated using standard logic voltage levels. Furthermore, ferroelectric memories are significantly faster than floating-gate memories, require less power to program, and can be reprogrammed many more times by several orders of magnitude (between 10.sup.10 and 10.sup.15 read/write cycles for existing memories). As such, ferroelectric memory is a rapidly developing technology in which much research and product development is currently being conducted.
Most ferroelectric memory development efforts to date have focused on memory chips and blocks of embedded memory. However, many common system and integrated circuit designs would also benefit greatly from the availability of autonomous non-volatile memory bits. Some potential uses include, but are not limited to, failed address storage for memory redundancy, post-production trimming of programmable current sources, logic circuit backup, and non-volatile registers. Previously, prior art circuits have been designed which realize autonomous bits of non-volatile memory. In these designs, however, no consideration has been given to important load issues or latch timing considerations.
What is desired, therefore, is a non-volatile latch circuit in which these important load issues and latch timing considerations are fully addressed.